Thursday 12 December 2013

Input / Output Architecture

Input / Output Architecture



General  defination :
Any information or data that's entered or sent to the computer  to be processed is considered input and anything that is displayed from the computer is output.

Input :

 An input device is any hardware device that sends data to the computer, without any input devices, a computer would only be a display device and not allow users to interact with it, much like a TV.

by : wan nur ulaiya


  • Scanner
  • Webcam
  • Digital Camera
  • Mouse ,touchpad or pointing device
  • Keyboard
  • Gamepad, Joystick,Paddle,Steering wheel

       








Output :

 Any peripheral that receives or displays output from a computer.


  • Monitor
  • 3D printer
  • Headphones
  • Speakers
  • Projectors
  • Plotters



Tip:***
 Keep in mind that drives such as a CD-ROMDVD, and a Floppy diskette drive may be capable of sending the computer information, but they are not output devices. These devices are considered storage devices.

Sound Output

Computers also produce sound output, ranging from simple beeps alerting the user, to impressive game sound effects, to concert quality music. High quality audio output from a PC usually requires a sound card in one of the expansion slots, connected to a set of good quality external speakers or headphones.
 A sound card is an example of a multimedia output device (as is a monitor that can display graphics).



      Explain I/O module and its usage?
Input-output interface provides a method for transferring information be­tween internal storage 
and external I/O devices.Peripherals connected to a computer need special communication links
 for interfacing them with the central processing unit.

                                            Purpose communication link : 

 to resolve the differences that exist between the central computer and each peripheral.

                                                                                                                                                                                                                                                                     by : nor izzati







1.  Peripherals are electromechanical and electromagnetic devices and their manner of operation is 
     different from the operation of the CPU and memory, which are electronic devices. Therefore, 
     a conversion of signal values may be required.

2.  The data transfer rate of peripherals is usually slower than the transfer rate of the CPU, 
     and consequently a synchronization
     mechanism may be needed.

3.  Data codes and formats in peripherals differ from the word format in the CPU and memory.

4. The operating modes of peripherals are different from each other and each must be controlled so as 
    not to disturb the operation of other peripherals connected to the CPU.








•         Interface to CPU and Memory
•       Interface to one or more peripheral










•            Control & Timing
•         CPU Communication
•         Device Communication
•         Data Buffering
•         Error Detection








·         Check status device
·         Tells status
·         Request for data transfer
·         Gather & transfer data to CPU







·         Command decoding
·         Exchange data ( Module to  CPU)

·         Report status
·         Address recogniction for device attach






·             Command
·         Status information
·         Transfer data







·         To overcome speed mismatch







·         Paper jam / Bad data / Damage data & etc.


by : siti hajar



    
•         CPU checks I/O module device status

•         I/O module returns status
•         If ready, CPU requests data transfer
•         I/O module gets data from device
•         I/O module transfers data to CPU
•         Variations for output, DMA, etc.



 




•          Hide or reveal device properties to CPU
•         Support multiple or single device
•         Control device functions or leave for CPU
•         Also O/S decisions
e.g. Unix treats everything it can as a file








•           Programmed
•         Interrupt driven
•         Direct Memory Access (DMA)









  • – Behavior: input, output, storage
  • – Partner: human or machine
  • – Data rate: bytes/sec, transfers/sec
  •  I/O bus connection may become the bottleneck.

***I/O may become a bottleneck, especially with fast CPUs.
***Example: increase CPU speed by 10 and double I/O speed.









Dependability is important
Particularly for storage devices

Performance measures
Latency (response time)
– Throughput (bandwidth)
– Desktops & embedded systems

Mainly interested in response time & diversity of devices
– Servers

Mainly interested in throughput & expandability of devices








Need interconnections between:

◦CPU, memory, I/O controllers

Bus :   Shared communication channel


Bus is simply a common set of wires that connect all the computer devices and chips together.
Some of these wires are used to transmit data. Some send housekeeping signals, like the clock pulse.
Some transmit a number (the "address") that identifies a particular device or memory location. 
The computer chips watch the address wires and respond when their identifying number is transmitted.
They then transfer data on the other wires.

#caution : But bus is limited to wire lenght, no of connection.

Bus Types : ** Processor -Memory buses
                  ** I/O buses















by : siti nazirah







  • Data lines -carry address & data
  • Control lines - indicate data type & transaction
  • Synchronous - use bus clock & fixed protocol
  • Asynchronous - use request , solve clock and synchronization prob 








Polling and interrupt-driven I/O

◦CPU transfers data between memory and I/O data registers
◦Time consuming for high-speed devices

Direct memory access (DMA)

OS provides starting address in memory
◦I/O controller transfers to/from memory autonomously
◦Controller interrupts on completion or error

***DMA controllers are standard components in PCs








Serial

◦In band signaling
◦Bit oriented
◦Bit/byte word translation

Parallel

◦Byte word oriented
◦Out of band signaling
◦IDE, SCSI

                          I/O  vs. CPU Performance


Amdahl’s Law



◦Don’t neglect I/O performance as parallelism increases compute performance



#Example ~~

◦Benchmark takes 90s CPU time, 10s I/O time
◦Double the number of CPUs/2 years
 **I/O unchanged




Applications are increasingly run on servers

◦Web search, office apps, virtual worlds

Requires large data center servers

◦Multiple processors, networks connections, massive storage
◦Space and power constraints

Server equipment built for 19” racks
◦Multiples of 1.75” (1U) high

example ; - )

















by : robael adawiyah




















LANGUAGE OF THE COMPUTER 2



32-BIT CONSTANT
  • ·         Most constant are small
  • ·    For the occasional 32-bit constant
    lui rt, constant
Ø  Copies 16-bit constant to left 16 bits of rt
Ø  Clears right 16 bits of rt to 0
0000 0000 0111 1101
0000 0000 0000 0000
 lui $s0 , 61


0000 0000 0111 1101
0000 1001 0000 0000
ori $s0, $s0, 2304 


BRANCH ADDRESSING
  • ·         Branch instructions specify
  • ·    Most branch targets are near branch

op
rs
rt
constant or address
                 6 bits  5 bits  5 bits             16 bits
  • ·         PC-relative addressing

-  Target address = PC + offset × 4
-  PC already incrementedby 4 by this time


JUMP ADDRESSING

  • ·         Jump (j and jal) targets could be anywhere in text segment

op
address
                   6 bits     26 bits
  • ·     (Pseudo) Direct jump addressing


By : Robael




FALLACIES
  • ·         Powerful instruction

ü  Fewer instructions required
ü  Complex instructions are hard to implement
ü  Compilers are good at making fast code from simple construction
  • ·                  Use assembly code for high performance

ü  Modern compilers are better
ü  More lines of code => more errors and less productivity

PITFALLS
  • ·               Sequential words are not at sequential addresses
  • ·                 Keeping a pointer to an automatic variable after procedure returns

ü  Ex : passing pointer back via an argument
ü  Pointer becomes invalid when stack popped

By : Nazirah




DECODING MACHINE LANGUAGE


Ø  How do we convert 1s and 0s to assembly language and
      to C code?
  •  Machine language  assembly  C?

For each 32 bits:
i)    Look at opcode to distinquish between R- Format, JFormat, and I-Format
ii)  Use instruction format to determine which fields exist
iii) Write out MIPS assembly code, converting each field to name, register number/name,
      or decimal/hex number
iv)  Logically convert this MIPS code into valid C code. Always possible? Unique?

  • Decoding (1)

Here are six machine language instructions in
hexadecimal:
00001025hex
0005402Ahex
11000003hex
00441020hex
20A5FFFFhex
08100001hex
Let the first instruction be at address 4,194,304 ten
(0x00400000hex)
Next step: convert hex to binary

  • Decoding (2)

The six machine language instructions in binary:  
00000000000000000001000000100101 
00000000000001010100000000101010
00010001000000000000000000000011 
00000000010001000001000000100000 
00100000101001011111111111111111 
00001000000100000000000000000001
Next step: identify opcode and format
0
rs
rt
rd
shamt
funct
1, 4-62
rs
rt
immediate
2 or 3
target address


  • Decoding (3)

Select the opcode (first 6 bits) to determine the format:  
00000000000000000001000000100101 
00000000000001010100000000101010 
00010001000000000000000000000011 
00000000010001000001000000100000 
00100000101001011111111111111111 
00001000000100000000000000000001
Look at opcode: 0 means R-Format, 2 or 3 mean J-Format, otherwise I-Format
Next step: separation of fields R R I R I J Format:
0
rs
rt
rd
shamt
funct
1, 4-62
rs
rt
immediate
2 or 3
target address


  • Decoding (4)

Fields separated based on format/opcode:
0
0
0
2
0
37
0
0
5
8
0
42
4
8
0
+3
0
2
4
2
0
32
8
5
5
-1
2
1,048,577

 Next step: translate (“disassemble”) MIPS assembly

instructions R R I R I J Format:                                  
By : Wan Nur Ulaiya



ARM  & MIPS SIMILARITIES
  • ·   ARM : The most popular embedded core
  • ·   Similar basic set of instructions to MIPS


ARM
MIPS
Date announced
1985
1985
Instruction size
32 bits
32 bits
Address space
32-bit flat
32-bit flat
Data alignment
Aligned
Aligned
Data addressing modes
9
3
Registers
15 x 32-bit
31 x 32-bit
Input/output
Memory mapped
Memory mapped


COMPARE AND BRANCH IN ARM
  • ·         Uses condition codes for result of an arithmetic / logical instruction
  • ·         Each construction can be conditional

By : Nor Izzati


SOURCES