32-BIT CONSTANT
- · Most constant are small
- · For the occasional 32-bit constant
Ø
Copies
16-bit constant to left 16 bits of rt
Ø
Clears
right 16 bits of rt to 0
0000 0000 0111 1101
|
0000 0000 0000 0000
|
lui $s0 , 61
0000 0000 0111 1101
|
0000 1001 0000 0000
|
ori $s0, $s0, 2304
BRANCH ADDRESSING
- · Branch instructions specify
- · Most branch targets are near branch
op
|
rs
|
rt
|
constant or address
|
6 bits 5 bits 5 bits 16
bits
- · PC-relative addressing
-
Target
address = PC + offset × 4
-
PC
already incrementedby 4 by this time
JUMP ADDRESSING
- · Jump (j and jal) targets could be anywhere in text segment
op
|
address
|
6
bits 26 bits
- · (Pseudo) Direct jump addressing
By : Robael
FALLACIES
- · Powerful instruction
ü
Fewer instructions required
ü
Complex instructions are hard to implement
ü
Compilers are good at making fast code from
simple construction
- · Use assembly code for high performance
ü
Modern compilers are better
ü
More lines of code => more errors and less
productivity
PITFALLS
- · Sequential words are not at sequential addresses
- · Keeping a pointer to an automatic variable after procedure returns
ü
Ex : passing pointer back via an argument
ü
Pointer becomes invalid when stack popped
By : Nazirah
DECODING MACHINE LANGUAGE
Ø How do we convert 1s and 0s to assembly
language and
to C code?
For each 32 bits:
i) Look at opcode to distinquish between
R- Format, JFormat, and I-Format
ii) Use instruction format to determine which fields
exist
iii) Write out MIPS assembly code, converting each field to
name, register number/name,
or decimal/hex number
iv) Logically convert this MIPS code into valid C
code. Always possible? Unique?
- Decoding (1)
Here are six machine language instructions in
hexadecimal:
00001025hex
0005402Ahex
11000003hex
00441020hex
20A5FFFFhex
08100001hex
Let the first instruction be at address 4,194,304 ten
(0x00400000hex)
Next step: convert hex to binary
- Decoding (2)
The six machine language instructions in binary:
00000000000000000001000000100101
00000000000001010100000000101010
00010001000000000000000000000011
00000000010001000001000000100000
00100000101001011111111111111111
00001000000100000000000000000001
Next step: identify opcode and format
0
|
rs
|
rt
|
rd
|
shamt
|
funct
|
1, 4-62
|
rs
|
rt
|
immediate
|
||
2 or 3
|
target address
|
||||
- Decoding (3)
Select the opcode (first 6 bits) to determine the
format:
00000000000000000001000000100101
00000000000001010100000000101010
00010001000000000000000000000011
00000000010001000001000000100000
00100000101001011111111111111111
00001000000100000000000000000001
Look at opcode: 0 means R-Format, 2 or 3 mean J-Format,
otherwise I-Format
Next step: separation of fields R R I R I J Format:
0
|
rs
|
rt
|
rd
|
shamt
|
funct
|
1, 4-62
|
rs
|
rt
|
immediate
|
||
2 or 3
|
target address
|
||||
- Decoding (4)
Fields separated based on format/opcode:
0
|
0
|
0
|
2
|
0
|
37
|
0
|
0
|
5
|
8
|
0
|
42
|
4
|
8
|
0
|
+3
|
||
0
|
2
|
4
|
2
|
0
|
32
|
8
|
5
|
5
|
-1
|
||
2
|
1,048,577
|
||||
Next step: translate (“disassemble”) MIPS assembly
instructions R R I R I J Format:
By : Wan Nur Ulaiya
ARM & MIPS
SIMILARITIES
- · ARM : The most popular embedded core
- · Similar basic set of instructions to MIPS
ARM
|
MIPS
|
|
Date announced
|
1985
|
1985
|
Instruction size
|
32 bits
|
32 bits
|
Address space
|
32-bit flat
|
32-bit flat
|
Data alignment
|
Aligned
|
Aligned
|
Data addressing modes
|
9
|
3
|
Registers
|
15 x 32-bit
|
31 x 32-bit
|
Input/output
|
Memory mapped
|
Memory mapped
|
COMPARE AND BRANCH IN ARM
- · Uses condition codes for result of an arithmetic / logical instruction
- · Each construction can be conditional
By : Nor Izzati
SOURCES
- Lecture Note Computer Organization and Architecture
- http://www.youtube.com/watch?v=X31oowVQm6w
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